1. Field of the Invention
Embodiments discussed herein relate to a cooperative control method for mutually adjusting the current imbalance among the power semiconductor elements connected in parallel, and to current balance control devices, and a power module integrally including the power semiconductor elements and the current balance control devices.
2. Background of the Related Art
In power conversion devices, such as an inverter and an uninterruptible power source apparatus, power conversion is performed by switching and driving power semiconductor elements. In the power semiconductor element, the maximum value of the current which one power semiconductor element is capable of feeding is limited in terms of physical properties and technically, and therefore when a load current exceeding this limit is needed, a plurality of power semiconductor elements is connected in parallel to increase the current capacity.
FIG. 7 illustrates a switching circuit formed by connecting two power semiconductor elements in parallel, FIG. 8 illustrates the current changes when two power semiconductor elements perform switching, FIG. 9 illustrates an example of a timing detection circuit, and FIG. 10 is an explanatory view of the operation of the timing detection circuit.
Note that, FIG. 7 illustrates a case of an IGBT (Insulated Gate Bipolar Transistor) as the power semiconductor element. However, the power semiconductor element is not limited to this IGBT, but an MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is also commonly used. This switching circuit is constituted by connecting the collectors and the emitters of an IGBT 101 and an IGBT 102, and may constitute, for example, a high-side arm portion and low-side arm portion in a totem pole output circuit of a power conversion device.
The IGBTs 101 and 102 connected in parallel in this manner are turned on or turned off by a pulse-like gate voltage that is simultaneously applied to the gates thereof, respectively. At this time, when the current flowing into the collectors is designated as Ic, a current Ic1 flows into the IGBT 101 and a current Ic2 flows into the IGBT 102. Ideally, the current Ic is evenly distributed by the IGBTs 101 and 102 so as to satisfy Ic1=Ic2=Ic/2. However, in the transitional period of this switching operation, an imbalance may occur between the currents flowing into the IGBTs 101 and 102.
Such current imbalance is caused by a difference in the turn-on or turn-off time between the parallel elements due to the variations of the device characteristics (Vth, Vce_sat, and the like) and the like which the IGBTs 101 and 102 have, an asymmetry of the substrate layout, and the like. If a time difference occurs in the turn-on time when the current starts to flow and in the turn-off time when the current stops, between the IGBTs 101 and 102, a transitional current imbalance will occur between the IGBTs 101 and 102. For example, as illustrated in FIG. 8, assume that the IGBT 101 first started to flow and then a little later the IGBT 102 started to flow. In this case, at the turn-on time, the current flows only through the IGBT 101 and therefore in the period of a time delay difference Δtd, the current will concentrate on the IGBT 101 and a high current will flow therethrough. If current concentration occurs, then the current exceeding the maximum rating flows, though for a short time, so that the IGBT 101 might be destroyed or the element temperature might abruptly rise to significantly degrade the element characteristics.
Therefore, it is proposed that the current imbalance among a plurality of IGBTs provided in parallel is reduced (e.g., see Japanese Laid-open Patent Publication No. 2014-230307). In this Japanese Laid-open Patent Publication No. 2014-230307, the turn-on and turn-off times of each IGBT are detected, and the turn-on and turn-off times of an IGBT which is turned on earlier are controlled so that the time delay difference Δtd becomes zero, i.e., so that these times are delayed. For the purpose of this control, a variable gate resistor circuit is provided in a circuit which drives the gate of the IGBT and the resistance value of the variable gate resistor circuit is varied according to the time delay difference Δtd. Thus, a plurality of IGBTs which is connected in parallel and is simultaneously driven is capable of reducing the current imbalance among the IGBTs.
The turn-on and turn-off times of the IGBT may be detected by a timing detection circuit illustrated in FIG. 9. The timing detection circuit of FIG. 9 detects the turn-on and turn-off times of the IGBT 101, for example, but also in the other IGBT 102, the turn-on and turn-off times are detected, respectively, by a timing detection circuit having the same configuration.
This timing detection circuit includes a sense resistor Rs, a comparator 103, and a reference voltage source Vref. The IGBT 101 has a current sensing terminal that is formed by partially separating and partitioning the emitter region of the chip of the IGBT 101. A current corresponding to the area ratio between the current sensing terminal and the main emitter terminal will flow into this current sensing terminal as a sense current Is. This sense current Is flows to the ground through the sense resistor Rs connected to the current sensing terminal of the IGBT 101, so that a sensing voltage Vs proportional to the emitter current is generated between the both ends of the sense resistor Rs. This sensing voltage Vs is compared with a reference voltage source Vref by the comparator 103 and a signal Ipulse is output.
This signal Ipulse rises when the sensing voltage Vs exceeds the reference voltage source Vref and falls when the sensing voltage Vs falls below the reference voltage source Vref as illustrated in FIG. 10. The rising of this signal Ipulse provides the turn-on time of the IGBT 101, and the falling of the signal Ipulse provides the turn-off time of the IGBT 101. These times are sent to a non-illustrated control circuit, where it is compared with the times of the IGBT 102, and the resistance value of the variable gate resistor circuit is controlled so that the respective times match with each other. Thus, the turn-on and turn-off times of the IGBTs 101 and 102 connected in parallel will be aligned to reduce the current imbalance between the IGBTs 101 and 102.
As described above, when the number of power semiconductor elements connected in parallel is two, in the control circuit of each of the power semiconductor elements, the turn-on and turn-off times just need to be compared with the turn-on and turn-off times of the power semiconductor element of the connection party. However, if the number of power semiconductor elements connected in parallel is increased, cooperative control for mutually communicating information about the turn-on and turn-off times among all the power semiconductor elements is needed and therefore the sizes of the control circuits will increase, respectively.
Then, the examples of the method for reducing the current imbalance among a plurality of power semiconductor elements include a method for measuring the characteristics of the power semiconductor elements in advance and selecting and combining the power semiconductor elements having close characteristics from among these power semiconductor elements. This method takes a great amount of effort and time to select the power semiconductor elements having the uniform characteristics, and therefore is not the method suitable for power conversion devices to be mass-produced. Therefore, as the cooperative control method for reducing the current imbalance among a plurality of power semiconductor elements, a master-slave type cooperative control method is known.
FIG. 11 illustrates a master-slave type cooperative control method. Here, as one example, a case will be described where six power modules each including a power semiconductor element and its control circuit are connected in parallel.
The master-slave type is a form, in which one module among six power modules PM1 to PM6 connected in parallel is set as a master module and the other modules are set as slave modules to perform cooperative operation. The master module (here, the power module PM1) is connected to all the other slave modules (here, the power modules PM2 to PM6) to collect the timing information of turn-on and turn-off about all the slave modules. The master module calculates, from its own timing information and the collected timing information about the slave modules, the individual reference information for reducing a current imbalance, and transmits the calculated reference information to each corresponding slave module. The master module controls the current balance using the calculated reference information as a control target. The slave module controls the current balance using, as a reference, the reference information provided from the master module. Thus, a reduction of the current imbalance among all the power modules PM1 to PM6 is achieved.
In accordance with the master-slave type cooperative control, the master module detects the operation states of all the modules including the master module, and calculates, from the detected operation states, the reference information to be targeted by each module. Such calculation needs to be performed a number of times, the number being the same as the number of the power modules connected in parallel, and therefore becomes a heavy load on the master module, and additionally the configuration of the power modules becomes complicated.
Moreover, every time the number of parallel connections is increased, the master module needs a new communication line and new input/output terminals for a newly added slave module, and therefore there is a problem that the variation for each of the parallel connections needs to be prepared in advance.